Gold(i) complexes based on a 2,4,6-triarylphosphinine and a mesoionic carbene derivative have been prepared and characterized crystallographically. Although structurally related, both heterocycles differ significantly in their donor/acceptor properties. These opposed electronic characteristics have been exploited in Au(i)-catalyzed cycloisomerization reactions. For the conversion of the standard substrate dimethyl 2-(3-methylbut-2-enyl)-2-(prop-2-ynyl)malonate the results obtained for both Au-catalysts were found to be very similar and comparable to the ones reported in the literature for other carbene- or phosphorus(iii)-based Au(i)-complexes. In contrast, a clear difference between the catalytic systems was found for the cycloisomerization of the more challenging substrate N-2-propyn-1-ylbenzamide. A combination of the phosphinine-based complex and [AgSbF] or [Cu(OTf)] leads to a catalytic species, which is more active than the mesoionic carbene-based coordination compound. We attribute these differences to the stronger π-accepting ability of phosphinines in comparison to mesoionic carbenes. The here presented results show for the first time that phosphinines can be used efficiently as π-accepting ligands in Au(i)-catalyzed cycloisomerization reactions.

We could access for the first time a 5-phosphasemibullvalene derivative via quantitative and selective photochemical di-π-methane rearrangement from the corresponding phosphabarrelene. Due to the striking analogy between phosphorus and carbon, this hitherto unknown transformation of vinyl-phosphorus species provides the possibility to prepare novel, chiral and conformationally rigid organophosphorus cage compounds in a straightforward manner.

An iridium dihydride pincer complex [IrH 2-(POCOP)] is immobilized in a hydroxy-functionalized microporous polymer network using the concepts of surface organometallic chemistry. The introduction of this novel, truly innocent support with remote OH-groups enables the formation of isolated active metal sites embedded in a chemically robust and highly inert environment. The catalyst maintained high porosity and without prior activation exhibited efficacy in the gas phase hydrogenation of ethene and propene at room temperature and low pressure. The catalyst can be recycled for at least four times.

Reaction of the trivalent uranium complex [((Ad,MeArO)3N)U(DME)] with one molar equiv [Na(OCAs)(dioxane)3], in the presence of 2.2.2‐crypt, yields [Na(2.2.2‐crypt)][{((Ad,MeArO)3N)UIV(THF)}(μ‐O){((Ad,MeArO)3N)UIV(CAs)}] (1), the first example of a coordinated η1‐cyaarside ligand (CAs−). Formation of the terminal CAs− is promoted by the highly reducing, oxophilic UIII precursor [((Ad,MeArO)3N)U(DME)] and proceeds through reductive C−O bond cleavage of the bound arsaethynolate anion, OCAs−. If two equiv of OCAs− react with the UIII precursor, the binuclear, μ‐oxo‐bridged U2IV/IV complex [Na(2.2.2‐crypt)]2[{((Ad,MeArO)3N)UIV}2(μ‐O)(μ‐AsCAs)] (2), comprising the hitherto unknown μ:η1,η1‐coordinated (AsCAs)2− ligand, is isolated. The mechanistic pathway to 2 involves the decarbonylation of a dimeric intermediate formed in the reaction of 1 with OCAs−. An alternative pathway to complex 2 is by conversion of 1 via addition of one further equiv of OCAs−.

In this paper, the hardware implementation of a burst error channel and a burst erasure channel simulator in Cyclone II Field Programmable Gate Array (FPGA) is proposed. In telecommunications, a burst error channel is a data transmission channel in which errors occur in a contiguous sequence of symbols, such that the first and last symbols are in error and there exists no contiguous subsequence of m correctly received symbols within the error burst. An erasure channel is one in which each transmitted symbol is either received correctly or is corrupted so badly as to be considered erased. When the erasures are clustered together we refer to the channel as a burst erasure channel. Although software simulations are easy to set up to simulate a transmission channel behavior, they are very time consuming. In order to speed up the communication system performance evaluation process and the final parameter optimization design, direct hardware emulation is proposed and presented. The implementation can be easily extended to other FPGA architectures