As mobility products, such as smart phones, tablets and wearable devices, continue on the paths of both miniaturization and high performance, components and packaging are likewise driven to become smaller and thinner. In mobile devices, a thinner package is required, especially for the Application Processor and memory combination. The Package-on-Package structure can achieve module thinness by embedding a die (or dies) into a package and is thus attractive for reducing the height of an AP. The Die-Embedded and RDL structure has been in development as a package corresponding to POP structure. This structure has two characteristics of manufacturing method, based on the substrate manufacturing process. One is the RDL-first process, whereby the RDL is manufactured before die attachment. This process decreases the die loss from defects in the RDL formation. The other method is to manufacture the packages in panel form instead of wafer form. The key features of this structure are panel-form manufacturing and via connection between the substrate and the top-RDL. In IMAPS 2016, the Die Embedded and RDL structure on i-THOP®, which was used as the substrate was reported. The die-to-die inter connection was fabricated on i-THOP® for a 2.1D application. Both the die attachment and the RDL formation were successfully performed. The reliability tests proceeded. The results indicated that the i-THOP® with the Die Embedded and RDL structure can be applied to packaging of AP in mobile devices. The next challenge is to make a smaller package using the Die Embedded and RDL structure. To decrease the package area, a finer-pitch via connection that was less than the design rule of 200μm was evaluated. For reduction of package thickness, a thinner substrate, approximately 160μm thickness, was applied. The new test sample with these improvements was designed and proceeded to evaluation. The dimensions of the sample are 15 × 15 mm2 size and 340μm thickness (without solder ball), a 100μm-thick die was embedded and a one-layer of RDL was formed on the die. In this development, the warpage of the thin substrate after die attachment might be large, so there is an issue of package warpage and the handling of a thin substrate. In this report, results of low warpage structure design and development status of fine via connection formation are described.
The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.
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