Nowadays, the All-Digital Phase-Locked Loop (ADPLL) as a digital electronic circuit is applied in modern communication systems. The main components of ADPLL such as phase detector, loop filter and voltage controlled oscillator which are all digitally discussed in detail. On the other hand, sensitivity to parasitic mismatches in LC oscillators and the limitation of the robustness and the quantization noise cause trying to overcome these challenges by a VCO and also a delta-sigma digital to analog converter which are essential for this aim. A new quadrature oscillator topology which includes four low-Q series LC tanks in a ring structure is employed in this paper. In the following, low distortion delta-sigma MASH architecture includes the advantages and significant specifications to achieve better performance, is explained. The proposed idea relying on studies of ADPLL efforts unlike the most of the previous works uses a ring oscillator. With quadrature ring structure, an ideal condition of implementation is provided that keeps all the advantages of previous works and even better off. To confirm and evaluate the analysis, the proposed structure simulated using TSMC 0.18μm model technology. The results confirm the proposed idea of implementation and higher performance of this structure
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