We demonstrate 100 ns write/erase speed of single-walled carbon nanotube field-effect transistor (SWCNT-FET) memory elements. With this high operation speed, SWCNT-FET memory elements can compete with state of the art commercial Flash memories in this figure of merit. The endurance of the memory elements is shown to exceed 104 cycles. The SWCNT-FETs have atomic layer deposited hafnium oxide as a gate dielectric, and the devices are passivated by another hafnium oxide layer in order to reduce surface chemistry effects. We discuss a model where the hafnium oxide has defect states situated above, but close in energy to, the band gap of the SWCNT. The fast and efficient charging and discharging of these defects is a likely explanation for the observed operation speed of 100 ns which greatly exceeds the SWCNT-FET memory speeds of 10 ms observed earlier for devices with conventional gate oxides.

Single walled carbon nanotube field‐effect transistors (SWCNT FETs) are attributed as possible building blocks for future molecular electronics. But often these transistors seem to randomly display hysteresis in their transfer characteristics. One reason for this is suggested to be water molecules adsorbed to the surface of the gate dielectric. In this study we investigate the hysteresis of SWCNT FETs at different relative humidities. We find that SWCNT FETs having atomic layer deposited (ALD) HfO2 – TiO2 – HfO2 as a gate dielectric retain their ambient condition hysteresis better in dry N2 environment than the more commonly used SiO2 gate oxide. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

We demonstrate controllable and gate-tunable negative differential resistance in carbon nanotube field-effect transistors, at room temperature and at 4.2 K. This is achieved by effectively creating quantum dots along the carbon nanotube channel by patterning the underlying, high-kappa gate oxide. The negative differential resistance feature can be modulated by both the gate and the drain-source voltage, which leads to more than 20% change of the current peak-to-valley ratio. Our approach is fully scalable and opens up a possibility for a new class of nanoscale electronic devices using negative differential resistance in their operation.

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO 2 and TiO 2 in a triple-layer configuration, we achieve the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics.