All optical memory elements are considered to be essential building components for optical networks with high practicality and utility. In this paper, a feasible integrable scheme is presented for the realization of all optical shift register, which is basically a memory device, where the information is transferred from input to output based on the configurations either in serial or parallel upon a clock pulse. Shift registers are classified based on input-output configuration as serial input-serial output, serial inputparallel output, parallel input-serial output (PISO), and parallel input-parallel output. All optical shift register is designed using interconnected D flip-flop (DFF) memories that are driven by standard clock pulses. DFF is built using Mach-Zehnder interferometer-semiconductor optical amplifier based on all optical logic gates, which is then cascaded accordingly to design different types of 4-bit shift registers except for PISO which is designed as a 2-bit shift register. The entire design is simulated in optisystem and verified the data transfer through DFFs in various configurations. The speed of the circuit is the same as data rate. The proposed circuits are simulated up to data rate of 100 Gbps. K E Y W O R D S all optical logic gates, all optical shift register, D flip-flop, semiconductor optical amplifier
This paper deals with the basic of Power quality in power system. In addition basic definition and important concepts was discussed in simple way. This paper also covers the important power quality standards. In addition IEEE, IEC, SEMI and UIE Power quality standards are listed. This paper would be helpful for the UG and PG students to study about the basics of Power quality in electrical engineering.
Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.
Contingency analysis is a widely known feature in present day Energy Management System (EMS).The purpose of this strength gadget evaluation feature is to offer the operator records approximately the static security. Contingency analysis of electricity gadget is a major pastime in power device planning and operation. In fashionable an outage of any person of transmission line or transformer might also result in over hundreds in other branches and/or unexpected machine voltage upward push or drop. Contingency evaluation is used to calculate violation. This paper shows the instance on IEEE-14 bus system which offers statistics of violation & remedial action to do away with violations. Exact studies had been completed to work out the contingency plans.
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