The development of IC integration technologies leads
to an extensive use of memories and buffers in different memory
intensive applications. Therefore, probability of occurrence of
fault in every single read and writes operation is increased in
Memory BIST (MBIST). There were many testing approaches
that were developed for efficient testing and diagnosis of fault.
However, all algorithms are not strengthened enough to detect all
possible faults that may be present due to fabrication errors or
environmental disturbance. Keeping this in mind and taking the
possibility of development of efficient algorithm a hybrid memory
testing algorithm is presented. To overcome those drawbacks,
pipelining based MBIST designed to detect the all the types of
memory faults by utilizing March-C testing algorithm. By
introducing the Pipelining approach, majorly path delays are
reducing. The proposed architecture designed and verified using
Xilinx ISE environment under various testing methods with
respect to the different category of memories. The simulation and
synthesis results shows that the proposed method shows the
enhanced performance with the hardware resource utilization
and delay consumption compared to the conventional
approaches.
Adders being core building blocks in several VLSI circuits like microprocessors, ALU's etc. performance of adder circuit extremely affects the capability of the system. during this paper we tend to present the design and performance of Parallel Self-Timed Adder. it's supported a algorithmic formulation for acting multibit binary addition. The operation is parallel for those bits that don't would like any carry chain propagation. A sensible implementation is provided in conjunction with a completion detection unit. The implementation is regular and doesn't have any sensible limitations of high fanouts. The planned work principally geared toward minimizing the amount of transistors and estimation of varied parameters viz., area, power, delay for pasta. we've got conjointly designed four bit pasta as an example of planned approach. Simulations are performed exploitation MICROWIND three.1software and DSCH tool in 45nm CMOS technology that verify the utility and superiority of the planned approach over existing asynchronous adders.
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