This paper presents a VHDL based method that enables the logic simulator to estimate the longest and the shortest path delays of all signals in the circuit with only one run of the logic simulator. The method is verified for ISCAS'85 benchmark circuits and for one particular embedded sequential circuit. It is extremely efficient and appropriate in the early phases of the design process where timing analysis needs to be repeated as the circuit is optimized or redefined.

No abstract

No abstract

No abstract

No abstract