The fortunes of signal processors are directly related to progress in integrated circuit technology. This technology has experienced recent advances in logic design density and increased clock rates that will have significant impact on the performance of signal processors for the next 4 to 5 years. The objective of this paper is to develop an architecture that is matched to the computational requirements of a typical RADAR system and show how it can be implemented with these new devices. An analysis has been conducted to determine the relationship beteen multiplications, additions, and memory accesses for those algorithms requiring the highest data throughput including an adaptive array process. An architecture for a signal processing engine is then developed that is matched to the relative ratios for these functions. This signal processing engine is then sized using configurable gate array integrated circuits to implement each of its major functions. Finally, an estimate is made of the number of engines required to process these algorithms.
Sign bit compression in fixed-point numbering systems can improve the dynamic range and round-off noise for signal processing algorithms. This paper analyses non-standard compression factors (CF) for compressed fixed-point data formats, where sign bit compression is performed on each individual fixed-point number. Although these compression techniques are applicable to other fixed-point formats, the compressed two's complement data format is selected for illustration. A brief background on compressed two's complement is provided. Obvious compression factors are powers of two due to binary formatting, but compression factors other than standard powers of two are presented. Compression factors of 3 and 5 are analysed in greater detail. Motivation for and advantages of non-power-of-two compression factors are identified.
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