-This contributioii presents the four phases of a project aiming at the realizatioii in VLSI of a digital audio equalizer with a linear phase characteristic. Tlie first step includes the identification of tlie system requirements, based on experience arid (psycho-acoustical) literature. Secondly, the signal processing algorithms coiistitutiiig the global design of tlie equalizer are coinputer siiiiulated. Tlie third step iiicludes tlie realization of tlie equalizcr design using one or more programmable DSP's. In order to niiiiiinize tlie iiiiiiiber of DSP chips necessary for the realization, tliis step reqiiircs tlic optimization of the structure and niappirig of the algoritliin oii tlie resources of tlie DSP. The number of processor cycles is crucial iii this optiniizatioii. The purpose of tlie resulting prototype is to test and to validate in a digital audio erivironrneiit the specificatioii generated iii tlic first step. Tlie programmability of the DSP's allows for specification cliaiiges at this stage of the project. The fourth step is tlie VLSI iiiiplciiiciitatioii of tlie validated algorithm of the previous pliase. For tliis purpose the structure of tlie algorithm is optimized in order to take fill1 advantage of tlie silicoii resources. Speed and required area are tlie crucial parameters in this optiniization. The final step includes tlie testiiig of tlie coiripleted chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will enipliasizc tlie algoritliinic and design considerations together with tlie results.
Some image processing applications (e.g. computer graphics and robot vision) require the rotation, scaling and translation of digitized images in real-time (25-30 images per second). Today's standard image processors can not meet this timing constraint so other solutions have to be considered. This paper describes a multi-ASIC solution which is capable of doing the image processing tasks in real-time. The first ASIC is a so-called affine transformer which calculates a one-dimensional coordinate every 25 ns. The second ASIC is a bilinear interpolator which calculates an interpolated value from four known surrounding values, again every 25 ns. This ASIC is designed in a modular setup which results in a flexible accuracy of the interpolation. If more accurate interpolation is required, another ASIC (containing an interpolation stage) is used. In this way for each application a proper accuracy is implemented, reaching optimal silicon area utilization and desired accuracy of interpolation. Using two affine transformers (for obtaining a two dimensional coordinate pair) and an interpolator, one can build a system which can translate, rotate and scale an image of size 1024 9 1024 in real-time (25-30 images per second). In this paper the system as well as the design of the ASICs are presented.
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