A method for wireless, non-contact testing of semiconductor wafers is presented. The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card and the device under test (DUT) on a wafer. The probe consists of a CMOS device with micro antenna structures and transceiver circuits. Each antenna and transceiver circuit is capable of probing one input/output (I/O) site on the DUT. Each I/O site on the DUT is connected to a single antennae and transceiver circuit, which is designed into the DUT. The antennae and transceiver circuits can be incorporated into the DUT without any impact on performance or real estate. The main advantage of non-contact wafer probing is higher reliability (less retest, no pad scrub marks), added functionality (higher test frequencies at higher pin densities), and increased throughput (higher parallelism, reduced alignment tolerance, less maintenance, and less downtime). The wireless probes interface to standard automated test equipment (ATE) while all antenna structures and electronics needed on the DUT are fully CMOS compliant.
The small-signal analysis shows that the MOS Colpitts oscillator is described by a third order characteristic equation. The procedure for finding the second order approximation is defined, and the solution corresponding to this approximation is found. Then the equations for transistor transconductance describing function are analyzed, and the design procedure corresponding to the "convenient" operation point is given. The same equations are also used for the analysis of amplitude stability in this oscillator. It is shown that the amplitude self-modulation (squegging) in the considered oscillator is absent for any conducting angle of the transistor.
An area-efficient multistage 3.0-to 8.5-GHz ultrawideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm 2 . The measurement results show a power gain S21 of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than −10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V. Index Terms-Active inductor (AI), CMOS, low-noise amplifier (LNA), shunt peaking, ultrawideband (UWB).
A tunable CMOS active inductor is presented. The circuit uses a crosscoupled pair of transistors providing positive feedback for enhanced quality factor. The circuit is biased with a controllable current source varying the feedback and tuning the inductor. The proposed inductor is designed and simulated in a 90 nm digital CMOS process. It shows a wide-frequency range inductive impedance and a very high resonance frequency. By cascading two inductors, a wideband filter/ amplifier is designed to characterise the inductor performance.
A fully-active low-noise amplifier (LNA) for ultrawideband application is presented. Passive on-chip inductor of conventional LNA design is replaced by low-noise active inductor, significantly reducing the total chip area of the proposed CMOS LNA. The core LNA circuit is a cascoded common-source amplifier loaded with an active inductor. Two buffer stages are used to provide the required input and output impedance matching. The amplifier is designed and simulated in 0.13-μm RF CMOS process. It exhibits a forward gain (S21) of 11.2 dB, a noise figure (NF) of 2.2-4.0 dB, and return losses (S11 and S22) of less than -10 dB over the frequency range of 2.0 to 11.2 GHz while consuming only 13.5mW from a power supply of 1.5 V. The proposed amplifier occupies 0.09mm 2 of chip area.
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