THIS PAPER will describe a programmable 16b fixed-point Digital Signal Processor (DSP) with an instruction cycle time of 60ns. A 51mm2 chip was processed using an advanced l.Opm, twin-tub, double level metal, CMOS technology; Figure 1. The processor is an enhanced architecture, incorporating an on-chip instruction cache memory for vector operations. A full custom design methodology was employed to design and verify the circuit design and layout.Unit (DAU) is instruction configurable as a 2-stage multiply/ accumulate or a 1-stage ALU. The multiplyladd signal processing data path consists of a 16 x 16 full precision two's complement parallel multiplier and 36b adder feeding two 36b accumulators. Product bit alignment shifter and saturation protection are provided t o simplify programming. Microprocessor style operations utilize the ALU data path that bypasses the multiplier with 1 6 or 32b data to a 15 function ALU and an 8 function shifter, with 4 shifts to both right and left. A set of conditional accumulator functions perform nonlinear signal operations and assist in the performance of many algorithms.An on-chip memory includes 2048 x 1 6 words of ROM for instructions and fixed coefficients, and 512 x 1 6 words of RAM for variable data. An internal ROM can be replaced with a larger external memory of 64K words for full speed prototyping, or for applications that require either frequent program modification or more memory than provided on-chip. Two addressing units support high-speed, register-indirect memory addressing with post-modification. Four address registers can be used for either read or write addresses t o the RAM without restrictions. Modulo addressing of arbitrary length and memory organization is supported. One address register is dedicated to the ROM for table look-up.double buffering and interfaces with codecs, time division multiplexed data, and to other DSPs in a zero-chip multiprocessor Figure 2 is a block diagram of the DSP. The Data Arithmetic The DSP includes two I/O ports. A Serial I/O port (SIO) provides Technology for Logic and Custom VLSI Applications", I E E E 'Tran, A., et. al., "Device Characteristics of a l.Om CMOS Custom Integrated Circuit Conference; 1986. environment. A Parallel I/O port (PIO) is capable of operatingas a bus master or slave for 8 and 16b interfaces. Communication with DSPs, microprocessors, or other 1/0 peripherals is supported. Both the SI0 and the PI0 include a user-maskable interrupt capability for automatic IjO handling. The processor is packaged in an 84-pin plastic or ceramic chip carrier. Many signal processing algorithms consist of repetitive multiply/accumulate instruction sequences. In principle, three busses (instruction, data and data) and three memories are required to execute these operations in, a single cycle. Because of the repetitive nature of the algorithms, a simpler dual bus architecture was chosen for stores and replays of the repeated instructions from a small 15-word cache memory; Figure 3. This memory structure allows parallel access of ins...
A new digital signal processor (the DSP32C) has been developed which performs 32-bit floating point operations at a rate of 25 MFLOPs and can be programmed using a standard C compiler. This paper presents an overview of the architecture and instruction set with emphasis on the enhancements over its predecessor, the DSP32. The perfommce is expressed with common signal processor benchmarks. The application development environment is described which highlights the C compiler and hardware development system. Finally, an application example iuustrates the power and ease-of-use of this DSP.
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