No abstract

An n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible to typical production line processes. The simulation results show an excellent agreement to experimental data.We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0 . 5~. The short channel effects have been also minimized. A unique self-aligned silicidation technology which has been developed to reduce the increased resistance of down-scaled junctions is also presented.

No abstract

A simplified version of BOX isolation technology is described. The new process has been greatly simplified over the original BOX by introducing an additional non-critical masking step. The body effect o b s e r v e d i n n a r r o w c h a n n e l d e v i c e s i s r e d u c e d i n t h e n e w s t r u c t u r e . T h e c a p a c i t a n c e m e a s u r e m e n t o n d i f f u s e d junctions in BOX structure shows smaller c o n t r i b u t i o n s f r o m d i o d e p e r i m e t e r a s compared to LOCOS structure. Hot electron reliability of small geometry MOSFETs has been also studied and the results are presented and discussed.

No abstract