The purpose of this study is to analyze the operation and design of symmetrical and asymmetrical multilevel inverter structures with reduced number of switching devices. In this study, the term of conventional inverter is defined as a single cascaded inverter. Specifically, the inverter operates in three complete loops and only produces 2-level and 3-level of output voltages. Usually, cascaded structure suffers from the high total harmonic distortion. Thus, by considering multilevel structure of inverter, low total harmonic distortion reduction and voltage stress reduction on switching devices can be archived. Sinusoidal pulse width modulation and modified square pulse width modulation are used as modulation techniques in switching schemes of the designed multilevel inverters. The findings indicate that, the designed multilevel structure cause low total harmonics distortion at the output voltage. Furthermore, the asymmetrical structure is producing the same output voltage levels with reduced number of switching devices compared to the symmetrical structure is experimentally confirmed. The findings show that the total harmonic distortion for 7-level (symmetrical) and 9-level (asymmetrical) are 16.45% and 15.22%, respectively.

This paper discusses the current total harmonic distortion (THDi) and voltage ripple minimization of SEPIC converter based on parameters design optimization. This conventional PFC SEPIC converter is designed to operate in discontinuous conduction mode in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Meanwhile, the ranges of duty cycle for buck and boost operations are between 0

This paper presents parameters analysis of 4-level capacitor-clamped boost converter with hard-switching and soft-switching implementation. Principally, by considering the selected circuit structure of the 4-level capacitor-clamped boost converter and appropriate pulse width modulation (PWM) switching strategy, the overall converter volume able to be reduced. Specifically, phase-shifted of 120° of each switching signal is applied in the 4-level capacitor-clamped boost converter in order to increase the inductor current ripple frequency, thus the charging and discharging times of the inductor is reduced. Besides, volume of converters is greatly reduced if very high switching frequency is considered. However, it causes increasing of semiconductor losses and consequently the converter efficiency is affected. The results show that the efficiency of 2-level conventional boost converter and 4-level capacitor-clamped boost converter are 98.59% and 97.67%, respectively in hard-switching technique, and 99.31% and 98.15%, respectively in soft-switching technique. Therefore, by applying soft-switching technique, switching loss of the semiconductor devices is greatly minimized although high switching frequency is applied. In this study, passive lossless snubber circuit is selected for the soft-switching implementation in the 4-level capacitor-clamped boost converter. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation.

This paper presents the comparison of resonant and passive lossless snubber circuits implementation for DC-DC boost converter to achieve soft-switching condition. By applying high switching frequency, the volume reduction of passive component can be achieved. However, the required of high switching frequency cause the switching loss during turn-ON and turn-OFF condition. In order to reduce the switching loss, soft-switching technique is required in order to reduce or eliminate the losses at switching devices. There are various of soft-switching techniques can be considered, either to reduce the switching loss during turn-ON only, or turn-OFF only, or both. This paper discusses comparative analyses of resonant and passive lossless snubber circuits which applied in the DC-DC boost converter structure. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation. The results show that the efficiency of resonant circuit and passive lossless snubber circuit are 82.99% and 99.24%, respectively. Therefore, by applying passive lossless snubber circuit in the DC-DC boost converter, the efficiency of the converter is greatly increased. Due to the existing of an additional capacitor in soft-switching circuit, it realizes lossless operation of DC-DC boost converter.

This study presents the evaluation of the proposed optimum 4-level capacitor-clamped DC-DC boost converter (CCBC) for high power density achievement by using Pareto-Front method. The 4-level CCBC with considering high switching frequency can greatly reduce the inductor size and volume. High switching frequency caused the switching devices to suffer high semiconductor losses. Consequently, the cooling device volume is increased as well. Thus, this study presents softswitching technique in the 4-level CCBC for semiconductor losses reduction. The combination of optimum design of inductor, improvement of circuit structure and soft-switching technique may lead to the highest power density of the converter. A 400 W of the 4-level CCBC converter is designed and experimentally verified. The results show that the inductance and inductor volume required in the 4-level CCBC is reduced by 88.89 and 80.75%, respectively. Besides, Pareto-Front curve shows the highest power density of soft-switching technique with the proposed 4-level CCBC is 6.51 kW/dm 3 at 800 kHz of switching frequency with efficiency of 97.20%.