Forward error correction (FEC) coding is evaluated, for enhancement of reliability and information throughput on power line communication channels. Rate one-half self-orthogonal comlutimal codes with maprity logic decoding were considered. A (2, 1,6) code with bit interleaving to degree 7 was particularly ell edive, and was implemented as a VLSl microelectronic chip.Extensive bit error rate and packet error rate tests on inbuilding power line links showed coding gains in excess of 15 dB at 1 O9 channel error rates. Tests were conducted at data rates from 1.2 to 28.8 kbit/s.
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