We present a validation and test methodology for a non-deterministic system, namely a True Random Number Generator (TRNG). The TRNG testing methods at Intel have matured over time, and what we present here is the 3rd generation methodology used in our latest chipset products. In addition to well known DFT and DFV techniques, testing of a TRNG requires rigorous statistical analysis to determine its proper operation. Known published works and standards don't address the TRNG testing and validation issues in high volumes or their recommendations are impractical in real manufacturing constraints. We present a practical statistical methodology for TRNG testing in a high volume manufacturing environment. Its validity was proven by testing a 65-nm CMOSbased TRNG design to meet NIST standards. Our methodology can be extended to the testing of similar non-deterministic systems.
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