A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118[Formula: see text][Formula: see text]W, with a delay of 606 ps, with an area of 33.1[Formula: see text][Formula: see text]m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage [Formula: see text][Formula: see text]V, input signal frequency [Formula: see text][Formula: see text]MHz is used. This 1-bit FA is designed and implemented using Cadences' 90[Formula: see text]nm “generic-process-design-kit” (GPDK).
This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.
The design of an air quality monitoring system is a recent trend and emerging research topic using IoT and wireless sensor technology. The massive number of automobiles entering metropolitan areas contributes to increased air pollution and lower air quality, which leads to serious health problems. The paper’s primary goal is to introduce a vehicular pollution monitoring system model that can detect and measure pollutants like carbon monoxide and smoke produced by automobiles. The proposed module consists of sensors that can detect the pollutants, carbon monoxide, and smoke released by a vehicle. A Node Micro-Controller Unit (NodeMCU) will work as the brain of the sensor node and communicator with the server through wireless fidelity. The suggested system model can monitor automobile pollution, and if any vehicle exceeds a certain threshold value, it will be reported to the traffic department and the owner of the vehicle. The proposed system model is straightforward and simple, and it is predicted to be inexpensive.
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