Ordered gallium arsenide (GaAs) nanowires are grown by molecular-beam epitaxy on GaAs (111)B substrates using Au-catalyzed vapor–liquid–solid growth defined by nanochannel alumina (NCA) templates. Field-emission scanning electron microscope images show highly ordered nanowires with a growth direction perpendicular to the substrate. The size (i.e., diameter) distribution of the wires is drastically narrowed by depositing the gold catalyst through an NCA template mask; this narrows the size distribution of the gold dots and arranges them in a well-ordered array, as defined by the NCA template. The nanowire diameter distribution full width at half maximum on the masked substrate is 5.1 nm, compared with 15.7 nm on an unmasked substrate.

GaAs nanowires were grown on GaAs (100) substrates by vapor–liquid–solid growth. About 8% of these nanowires grew in 〈110〉 directions with straight, Y-branched or L-shaped morphologies. The role of strain-induced reduction in surface free energy is discussed as a possible factor contributing to the evolution of 〈110〉 nanowires. Kinking and branching is attributed to growth instabilities resulting from equivalent surface free energies for 〈110〉 growth directions. Transmission electron microscopy verified that 〈110〉 nanowires are defect free.

Catalyst-assisted growth of semiconductor nanowires has opened up several new and exciting possibilities for low-dimensional semiconductor structures. The authors review progress on the realization of quantum dots in semiconductor nanowires, and their characterization by transport spectroscopy. Emphasis is placed on the wide range electronic properties exhibited due to flexibility of the growth process in terms of nanostructure composition and size. Particular attention is placed on studies of spin in few-electron quantum dots.

The structure of wurtzite and zinc blende InAs–GaAs (001) core–shell nanowires grown by molecular beam epitaxy on GaAs (001) substrates has been investigated by transmission electron microscopy. Heterowires with InAs core radii exceeding 11 nm, strain relax through the generation of misfit dislocations, given a GaAs shell thickness greater than 2.5 nm. Strain relaxation is larger in radial directions than axial, particularly for shell thicknesses greater than 5.0 nm, consistent with molecular statics calculations that predict a large shear stress concentration at each interface corner.

A single localized charge can quench the luminescence of a semiconductor nanowire, but relatively little is known about the effect of single charges on the conductance of the nanowire. In one-dimensional nanostructures embedded in a material with a low dielectric permittivity, the Coulomb interaction and excitonic binding energy are much larger than the corresponding values when embedded in a material with the same dielectric permittivity. The stronger Coulomb interaction is also predicted to limit the carrier mobility in nanowires. Here, we experimentally isolate and study the effect of individual localized electrons on carrier transport in InAs nanowire field-effect transistors, and extract the equivalent charge sensitivity. In the low carrier density regime, the electrostatic potential produced by one electron can create an insulating weak link in an otherwise conducting nanowire field-effect transistor, modulating its conductance by as much as 4,200% at 31 K. The equivalent charge sensitivity, 4 × 10(-5) e Hz(-1/2) at 25 K and 6 × 10(-5) e Hz(-1/2) at 198 K, is orders of magnitude better than conventional field-effect transistors and nanoelectromechanical systems, and is just a factor of 20-30 away from the record sensitivity for state-of-the-art single-electron transistors operating below 4 K (ref. 8). This work demonstrates the feasibility of nanowire-based single-electron memories and illustrates a physical process of potential relevance for high performance chemical sensors. The charge-state-detection capability we demonstrate also makes the nanowire field-effect transistor a promising host system for impurities (which may be introduced intentionally or unintentionally) with potentially long spin lifetimes, because such transistors offer more sensitive spin-to-charge conversion readout than schemes based on conventional field-effect transistors.