We have performed positron annihilation experiments on CdTe films grown by vacuum evaporation at 220 °C on both plain glass and indium-tin-oxide-coated glass substrates. By checking the linearity of the valence annihilation parameter S versus the core annihilation parameter W we introduce a method to analyze the data which directly shows that the same vacancy defect can be present in all the films. By comparing the core annihilation parameter at the defect to that at the VCd vacancy we can identify this defect as the divacancy VCd-VTe. Its concentration in the films decreases from about 1018 to less than 1016 cm−3 after annealing in air at 400 °C for about 30 min. Chlorine doping seems to stabilize the divacancies.

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Forward bias recombination (current transport) mechanisms have been evaluated for thin film solar cells and correlated to the in-gap trap levels present. Here CdTe/CdS devices were chosen as an archetypal example of a modern thin film solar cell, and a set of devices with a range of design variables was used in order to reveal the full range of behaviours that may operate to limit current transport. Experimental current-voltage-temperature datasets were compared to mathematical models of transport, and the in-gap traps were evaluated by thermal admittance spectroscopy. The current transport mechanisms operating are presented on a temperaturevoltage diagram. Three regimes were identified: at 'intermediate' voltages, the behaviour was temperature dependent. From 300 K down to 240 K, thermally activated Shockley Read Hall recombination mediated by a 0.38 eV trap (V Cd ) dominated the transport. Between 200 and 240 K the transport was thermally activated but below 200 K the mechanism became dominated by tunnel assisted interface recombination. At 'low' voltages (and for all devices at all voltages when measured at T<200 K) band to band recombination is via multi-step tunnelling through in-gap states. At high voltage, the forward current is dominated by the well-known limiting effect of the back Schottky contact to the CdTe which is in reverse bias. The current transport behaviour is also correlated with the n-CdS thickness and CdCl 2 processing conditions, both of which are critical to device performance.