Data processing is a challenging problem in space applications. The limited bandwidth available for communication between satellites and the ground and the increasing resolution of scientific instruments make it virtually impossible to transfer all the data recorded on board. Although various mitigation strategies were developed, large amounts of on-board data are still lost. This paper presents a Field Programmable Gate Array (FPGA)-based architecture which is able to perform on-board nonlinear analysis of data and compute probability distribution functions of fluctuations. We propose two implementations for our solution, which can be used for space applications and also other computational contexts. On a spacecraft, the logic resources of the FPGA will typically be shared by several designs running various digital signal processing algorithms. That is why each algorithm should be designed in variants, optimized for different criteria, so that the entire group of algorithms makes an efficient usage of the FPGA resources. The proposed solution focuses on two major optimization criteria, area and speed, such that the FPGA resources are efficiently used. Also, the power consumption is at least two orders of magnitude less in comparison with classical software implementations. The solution was tested with both synthetic and real data and shows excellent results paving the way towards an application that can be ported on a space-grade FPGA.
This paper addresses the problem of performing time series analysis on-board a spacecraft, where the number of constraints is much bigger than for applications running in regular (i.e., ground-based) environments. An objective of modern spacecraft technologies designed for space exploration is to perform on-board data processing tasks, in order to increase the amount of data available for scientific analysis. Field Programmable Gate Array (FPGA) devices are considered as good candidates for hardware implementations of such systems. In order to optimize the usage of on-board resources, FPGAs share their resources between several digital signal processing (DSP) algorithms. In this paper, we describe the design and implementation of such an optimized design where two DSP algorithms are implemented on the same FPGA: (1) the power spectral density and (2) the multiscale probability distribution functions. The entire implementation process is described in detail, including a discussion about the main architectural choices. The proposed solutions focus on optimization of area, speed, and power. The tests performed, on both synthetic and real data, demonstrate the feasibility of our approach and constitute the first step toward porting the design on space-grade FPGAs.
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