A 12 parallel low voltage differential signaling (LVDS) transmitter fabricated in 0.13 μm CMOS is presented. Each LVDS channel can operate over 1.6 Gb/s and includes a programmable pre-emphasis circuit designed to reduce the data-dependent jitter (DDJ) caused by different lengths of PCB traces. Experimental results of the fabricated LVDS confirm the correct operation of the programmable pre-equalization circuit. The power consumption and area per channel is less than 20 mW and 0.084 mm 2 , respectively.
A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA), and 16 SAR ADC's. The chip includes (i) a programmable delay cell array to adjust the interleaved sampling phase, and (ii) a 12 Gbps low voltage differential signaling (LVDS) interface. These blocks make the fabricated ADC an excellent platform to evaluate mixed-signal calibration techniques, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show 33.9 dB of peak signal-to-noise-and-distortion ratio (SNDR) and 192 mW of power consumption at 1.2 V.
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