Arithmetic Logic Units (ALUs) are very important components in computer systems. They are digital circuits utilized to perform a wide variety of arithmetic and logic operations. Modern Central Processing Units (CPUs) contain powerful and complex ALUs. One such operation performed by ALUs is that of Multiplication. Multiplication scales one variable by another. This research involves the design, implementation and verification of a 4-digit BCD Multiplier Core with Similarity Investigator for path delay reduction. The system is implemented using Xilinx ISE 14.7, verified using ISim and Digilent Nexy3 toolkit and was utilized as the development platform. The research concluded that similarity investigation was capable of path delay reduction of up to 97% compared to that when no similarity investigation was applied. The system can conduct a maximum of 889 unique multiplication operations before facing diminishing returns as a result of the similarity investigation search procedure.
All in-class teaching in the Republic of Trinidad and Tobago, West Indies was suspended on Friday, 13th March 2020, because of the COVID-19 global health crisis. These restrictions remained for the commencement of the new academic year 2020-2021, which began in September 2020, thus jeopardizing the delivery of course content at the University of the West Indies, St. Augustine campus using the traditional in-class methodology. This paper presents an effective methodology for teaching and assessing laboratory-intensive courses during COVID-19 school restrictions. A mandatory level-two laboratory course of the Department of Electrical and Computer Engineering at the UWI was utilized as the basis of this study, which aimed at demonstrating that the methodology prevented student performance from degrading below what was experienced in the past five academic years. Feedback questionnaires were also administered to students, highlighting the key benefits they gained.
The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital electronic components through a hardware description with a minimal understanding of the VHDL language. This paper entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix Laboratory (MATLAB). Application Builder as the development platform. After development, the system went through unit testing and integration testing, after which acceptance testing was carried out. The results of the acceptance tests showed that the software is very effective in quickly generating VHDL code for ControlPaths.
First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.
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