Humans are complex organisms made by millions of physiological systems. Therefore, physiological activities can represent physical or mental states of the human body. Physiological signal processing is essential in monitoring human physiological features. For example, non‐invasive electroencephalography (EEG) signals can be used to reconstruct brain consciousness and detect eye movements for identity verification. However, physiological signal processing requires high resolution, high sensitivity, fast responses, and low power consumption, hindering practical hardware design for physiological signal processing. The bionic capability of memristor devices is very promising in the context of building physiological signal processing hardware and they have demonstrated a handful of advantages over the traditional Von Neumann architecture system in accelerating neural networks. Memristor networks can be integrated as a hardware system for physiological signal processing that can deliver higher energy efficiency and lower latency compared to traditional implementations. This review paper first introduces memristor characteristics, followed by a comprehensive literature study of memristor‐based networks. Physiology signal processing applications enabled by these integrated memristor networks are also presented in this review. In summary, this paper aims to provide a new perspective on physiological signal processing using integrated memristor networks.

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Neural architecture search (NAS), as a subfield of automated machine learning, can design neural network models with better performance than manual design. However, the energy and time consumptions of conventional software‐based NAS are huge, hindering its development and applications. Herein, 4 Mb phase change memory (PCM) chips are first fabricated that enable two key in‐memory computing operations—in‐memory multiply‐accumulate (MAC) and in‐memory rank for efficient NAS. The impacts of the coating layer material are systematically analyzed for the blade‐type heating electrode on the device uniformity and in turn NAS performance. The random weights in the searched network architecture can be fine‐tuned in the last stage. With 512 × 512 arrays based on 40 nm CMOS process, the PCM‐based NAS has achieved 25–53× smaller model size and better performance than manually designed networks and improved the energy and time efficiency by 4779× and 123×, respectively, compared with NAS running on graphic processing unit (GPU). This work can expand the hardware accelerated in‐memory operators, and significantly extend the applications of in‐memory computing enabled by nonvolatile memory in advanced machine learning tasks.

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