Failure Analysis (FA) plays an important role during silicon development and yield ramp up, helping identify critical test, design marginality and process issues in a timely and efficient manner. FA techniques typically rely on diagnosis callouts as a starting point for debug. Diagnostic algorithms rely on the error logs collected on production patterns which are generated to detect Stuck-at Faults (SAF) and Transition Delay Faults (TDF). Typically, SAF patterns screen out the static defects and TDF patterns test for transient fails. But often, we see cases where a SAF pattern shmoo is clean but the TDF pattern shmoo is a gross failure indicating a cell-internal static defect missed by the traditional SAF patterns. In this work, we will present our own developed User-Defined Fault Model, which targets cell-internal faults to explain unexpected silicon observations. An added advantage of the work can be seen in improving diagnosis results on the error logs collected using these targeted UDFM patterns. Since UDFM utilizes targeted fault excitation, the diagnosis algorithm results in better callouts. In this paper, we will also propose a custom diagnosis flow using our in-house UDFM to achieve better resolution. Three FA case studies will be presented to showcase the usefulness and effectivity of the proposed methods.
Hard functional and logic failures which are insensitive to temperature, voltage, or frequency have become increasingly difficult to debug in advanced technology nodes, especially when Photon Emission (PEM) analysis could not provide any leads and Dynamic Laser Stimulation (DLS) could not be used due to the nature of the failure (no pass/fail margin). Laser Voltage Imaging (LVI), which is an extension of the Laser Voltage Probing (LVP) technique, provides a visual map of active components that are toggling at a certain frequency. This technique is widely employed in scan chain debug due to its simplicity, efficiency, and accuracy. However, most of LVI applications in literature reviews only involve scan chain fault isolation. This paper will present alternative applications for LVI, apart from scan chain debug. One specific application is the debug of a broken signal path by sending a periodic signal as a stimulus to a GPIO pad and tracing the LVI signal through the path by frequency mapping. In this paper, the concept and methodology behind this fault isolation approach will be discussed in full detail. Furthermore, three case studies of different types of hard failures with different applications of LVI will also be presented: an IO functional failure, an ATPG (Automatic test pattern generation) SAF (Stuck At Fault) failure and a BSDL(Boundary scan description language) input interconnect failure, to illustrate how LVI could be deployed in fault isolation for those functional and logic hard failures.
Photon Emission Microscopy (PEM) analysis is one of the most common used FA techniques to identify the root cause of failures within ATPG scan logic due to its ease of setup and less invasive nature. While conducting photon emissions, the device is made to operate in the fail mode by running a production test vector to look for anomalous emissions or hot spots that could narrow down the area of interest (AOI) for subsequent Physical Failure Analysis (PFA). However, if there is no clue from emission analysis in the case of a hard failure with no sensitivity to voltage, frequency, or temperature, FA debug will be challenging. This paper shows how PEM analysis success may be further improved through logic state circuit study using a DFT ATPG diagnostic platform. Logic state truth table and its relative test pattern will be built based on the diagnostic data using in-house scripts, and the test program can then be changed to the required condition of the circuitry. With the altered logic state, new emission data can be collected, which could potentially reveal new clues to the investigation.
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