No abstract

No abstract

No abstract

This paper presents an analysis and comparison of Phase Locked Loop techniques used in grid utility applications to find the voltage vector angle generated from the supply voltages. The Phase Locked Loop (PLL) has a wide range of applications as Distributed Generation (DG), Flexible AC Transmission Systems (FACTS), static VAR compensators, cycloconverters, Active Power Filters (APF's) and others systems connected to the utility. The performance of these systems in grid connected applications is strongly influenced by the adopted PLL strategy. For this reason, the goal of the proposed paper is to present a comparison of different PLL-based techniques for utility applications to indicate the appropriate solution dedicated to a specific application. The criteria to compare the Phase Locked Loops techniques is the performance under distorted and unbalanced supply voltages.

A new stationary frame control scheme for threephase pulsewidth-modulation (PWM) rectifiers operating under unbalanced voltage dips conditions is proposed in this paper. The proposed control scheme regulates the instantaneous active power at the converter poles to minimize the harmonics of the input currents and the output voltage ripple. This paper's novelty is the development of a new current-reference generator implemented directly in stationary reference frame. This allows using proportional sinusoidal signal integrator (P-SSI) controllers for simultaneous compensation of both positive and negative current sequence components. No phase-locked loop (PLL) strategies and coordinate transformations are needed for the proposed currentreference generator. Experimental results are presented for a 20-kVA alternative current (ac)/direct current (dc) converter prototype to demonstrate the effectiveness of the proposed control scheme. A comparison with two other existing control techniques is also performed. Fast dynamic performance with small dc-link voltage ripple and input sinusoidal currents are obtained with this control scheme, even under severe voltage dips operating conditions.Index Terms-AC/DC converter, current-reference generator, voltage dips.

No abstract

This paper presents a frequency response analysis of current controllers based on selective harmonic compensation schemes for three-phase voltage-source shunt Active Power Filters (APFs). To perform this analysis, the time delay introduced by the inverter and the sampling is taken into account in the current controller closed loop transfer function. Doing this, the differences among the schemes are pointed out, demonstrating the importance and effectiveness of the delay compensation to maintain the whole system stability. In addition, the performance of each current controller is evaluated by means of the total harmonic distortion of the mains line current and time response for fast load variations. The main goal is to identify the most suitable solution in terms of current controllers based on selective harmonic compensation for an industrial implementation. All the considered current control schemes have been tested on the same digital platform. Experimental results are presented for a 25-kVA shunt APF prototype compensating a nonlinear inductive load. 

Fundamental-frequency and harmonic positive-and negative-sequence components detection is an important task for implementing power converters for renewable energy systems, uninterruptible power supplies, active power filters, dynamic voltage restorers, and also for power systems protection relays. Detection techniques of this kind are generally implemented in digital signal processor (DSP) with the execution time limited by the sampling period. The computational effort of the control algorithm can considerably increase the execution time, due to the sequential nature of processing in DSP. A promising technique for sequence components separation of three-phase signals is the so called the generalized delayed signal cancelation-phase locked loop (GDSC-PLL). Field programmable gate array's (FPGA's) capacity of exploring the parallelism of operations present in the GDSC-PLL is demonstrated in this paper through the mapping of this technique directly in hardware, allowing for a much shorter execution time than in DSP. The proposed architecture is presented, and the efficient detection of the fundamental-frequency positive-sequence with FPGA is demonstrated, with the obtained results compared with a traditional DSP implementation. In particular, the advantages and possibilities of the use of FPGA are demonstrated in comparison with the DSP. For this comparison, a metric for evaluating the capacity of complexity increase in application algorithms is proposed.Index Terms-Digital signal processor (DSP), field programmable gate array (FPGA), generalized delayed signal cancelation-phase locked loop (GDSC-PLL), phase detection, three-phase system.