Farside Explorer is a proposed Cosmic Vision medium-size mission to the farside of the Moon consisting of two landers and an instrumented relay satellite. The farside of the Moon is a unique scientific platform in that it is shielded from terrestrial radio-frequency interference, it recorded the primary differentiation and evolution of the Moon, it can be continuously monitored from the Earth-Moon L2 Lagrange point, and there is a complete lack of reflected solar illumination from the Earth. Farside Explorer will exploit these properties and make the first radio-astronomy measurements from the most radio-quiet region of near-Earth space, determine the internal structure and thermal evolution of the Moon, from crust to core, and quantify impact hazards in near-Earth space by the measurement of flashes generated by impact events. The Farside Explorer flight system includes two identical solarpowered landers and a science/telecommunications relay satellite to be placed in a halo orbit about the Earth-Moon L2 Lagrange point. One lander would explore the largest and oldest recognized impact basin in the Solar SystemExp Astron (2012) 33:529-585 531 the South Pole-Aitken basin-and the other would investigate the primordial highlands crust. Radio astronomy, geophysical, and geochemical instruments would be deployed on the surface, and the relay satellite would continuously monitor the surface for impact events.

No abstract

No abstract

In this paper, we report our experiences and findings on the design of a fault-tolerant bus architecture comprised of two COTS buses, the IEEE 1394 and the I2C. This fault-tolerant bus is the backbone system bus for the avionics architecture of the X2000 program at the Jet Propulsion Laboratory. COTS buses are attractive because of the availability of low cost commercial products. However, they are not specifically designed for highly reliable applications such as long-life deep-space missions. The X2000 design team has devised a multi-level fault tolerance approach to compensate for this shortcoming of COTS buses.First, the approach enhances the fault tolerance capabilities of the IEEE 1394 and I2C buses by adding a layer of fault handling hardware and software. Second, algorithms are developed to enable the IEEE 1394 and the I2C buses assist eacfi other to isolate and recovery from faults. Third, the set of IEEE 1394 and I2C buses is duplicated to further enhance system reliability. The X2000 design team has paid special attention to guarantee that all fault tolerance provisions will not cause the bus design to deviate from the commercial standard specifications. Otherwise, the economic attractiveness of using COTS will be diminished. The hardware and software design of the X2000 fault-tolerant bus are being implemented and flight hardware will be delivered to the ST4 and Europa Orbiter missions.

No abstract

No abstract

No abstract

Among the COTS applications in the X2000 architecture for deep-space missions, the use of commercial bus standards is the highest-payoff COTS application since a bus interface has a global impact on system cost and capability. While COTS bus standards enable significant cost reductions, it is a great challenge for us to deliver a highly-reliable long-term survivable system employing COTS standards that are not developed for mission-critical applications. The essence of our solution to the problem is to exploit the pertinent standard features of a COTS product to circumvent its shortcomings, including those standard features that are not originally designed for reliability purpose. In this paper, we discuss our experiences and findings on the design and assessment of an IEEE 1394 compliant fault-tolerant bus architecture. We first derive and qualitatively analyze a "stack-tree topology" that not only complies with IEEE 1394 but also enables the implementation of a fault-tolerant bus architecture without node redundancy. We then present a quantitative evaluation that demonstrates significant reliability improvement resulting from the COTS-based fault tolerance. We also describe the benefits from using COTS intellectual properties for hardware implementation of the bus architecture and discuss our general approach to COTS-based fault tolerance.