Image compression has been a widely researched field for decades. Recently, there has been a growing interest in using basis selection algorithms for signal approximation and compression. Signal approximation using a linear combination of basis from an over-complete dictionary has proven to be an NP-hard problem. By selecting a smaller number of basis than the span of the signal, we achieve glossy compression in exchange for a small reconstruction error. For the past few decades orthogonal and biorthogonal complete dictionaries such as Discrete Cosine Transform (DCT) or wavelets were the dominant transform domain representations of signals. Over-complete dictionaries have been intensively studied and successfully applied to various application such as image de-noising, compression etc. The DCT and wavelet based compression methods suffer from blocking and ringing artefacts and also they are unable to capture the directional information. So, in this context an investigation has been made by using sparse coding method by Orthogonal Matching Pursuit (OMP) algorithm. In this proposed work, conventional DCT can be replaced by a set of trained dictionaries. For dictionary construction we have used a combination of DCT and Gabor basis and to encode the trained dictionary elements we have employed OMP algorithm. Experimental results demonstrate that the proposed method provides gains in Rate Distortion (RD) performance and improvements in perceptual quality.
Context-based adaptive variable-length coding (CAVLC) is an important feature of the latest video coding standard H.264/AVC. The coding technique using conventional CAVLC based on area efficient design, the second is on low power design architecture will lead to low throughput. In this paper, an efficient CAVLC design is proposed. The main concept is the FPGA based pipelining scheme for parallel processing of two 4x4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bit stream. Our block based pipelined architecture doubles the throughput of CAVLC at high bit rates. The proposed architecture can make a real time processing of 1920X1080 @ 30fps. With the synthesis constraint of a 200MHz clock using altera cyclone-II FPGA.
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