The Al/CeO2/Si metal–insulator–semiconductor (MIS) structure showed a capacitance–voltage (C–V) hysteresis, which could be controlled by variation of the CeO2 thickness. For a sample with 3000 Å CeO2, hysteresis width as high as ∼1.8 V was obtained. For nonvolatile field-effect transistors, the Al/CeO2/Si MIS structure with a reliable and controllable C–V hysteresis could be an alternative to metal–ferroelectric–semiconductor structures containing unstable, multicomponent ferroelectric materials.
In this paper, a study on middle-of-line (MOL) process on transistor performance and reliability was presented based on 300mm experimental data. The major MOL parameters that are affecting device performance and reliability are MOL thermal expense and mechanical stress from contact etch stop nitride liner. Based on the study, we had developed a robust 45nm gatelength CMOSFET for 90nm node high performance application. Aggressive gate length and gate dielectric scaling along with optimized MOL engineering has proven high performance devices similar to 65nm node CMOSFET [1].
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