Data pattem advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, were attributable to particle caused anomalous clock signals, or propagated transients[ 1] [2]. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flipflop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the preset flip-flops. Masking the clock logic on one of the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU.By introducing N2 gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET'S, a 24-26 MeVcm2mg LET threshold was deduced.Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm2/mg (283 MeV Cu at Oo) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not [3]. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive.
A. Introducu 'onCf-252 tests were performed on a bulk CMOS technology microprocessor, designed and fabricated using a radiation hardened CMOS p m s s . During the processor design, analysis of the flip-flops had indicated all SEU thresholds to be above the linear energy transfer (LET) levels obtainable from Cf-252 fission fragments. These have a maximum incident LET in silicon of 46MeV-cm2/mg, and maximum degraded LET'S in silicon, after penetrating to depths of interest (9-12pm. including surface dielectric layers), of about 35MeV-cm2/mg. Because of the confidence in the design analysis, SEUs were not expected in the Cf-252 environment. The tests were * Work supported under Honeywell IR&D Project No. 050501015.intended only to confirm the absence of upsets for LETS at and below 35MeV-cm2/mg, prior to the performance of comprehensive cyclotron tests scheduled several months later. In fact, the primary purpose of the Cf-252 test was to look for single particle latchup (SPL) susceptibility. Johnston and Hughlock have since shown Cf-252 to be a poor source of particles for SPL tests [4].
B. TestPmcedureThe microprocessor has built-in-test (BIT) functions, controlled by two mode select inputs. The BIT functions are called native fault test (IWQ modes. One NFT mode places all flip-flops into a serial scan path[5], forming a very long NFT register. Since all flip-flops are clocked, state changes are not propagated unless a clock signal is present. The contents of the NFT register can be serially loaded through one extemal pin and serially read through a second. Thus, all flip-flops are easily accessible via the two NFT register input and output pins, and clocked via the normal chip clock input pin.Exposures were initially conducted in vacuum, with a 5pCi C...