Instituting dimensional reductions in the layout of CMOS semiconductor chips can lead to unwanted conduction paths significant enough to impact the performance and reliability of the subsequent fabricated integrated circuit. Positive location and identification of the suspect areas is required for the determination of root cause and to enable corrective action to eliminate or minimize the unwanted conduction paths. Empirical methods have to be employed to identify suspect areas since EDA vendors do not have CAD tools sufficiently capable of identifying the suspect areas during the design phase of a complicated high performance integrated circuit.Applying varied thermal imaging procedures and analytical techniques on specially assembled bare chips with defined limited performance identified problematic chip substrate regions and subsequent current conduction through the substrate as the problem in those regions. Corrective chip design layout and assembly techniques were instituted to achieve the required isolation.Although corrective action was achieved through chip design layout modifications, an outline of the wafer processing technology employed will be presented to designate the questionable areas with possible fabrication alterations to avoid the conduction paths encountered.
High tolerance chip capacitors are at best expensive and at the worst unobtainable. When asked to custom build a small signal circuit containing close tolerance RC networks it became obvious that functional resistor trimming was unavoidable if suitable quantities were to be produced at the right price.The product which is shown in Figure is constructed by conventional thick film techniques. It uses a l"x 2" alumina substrate and attached com- 2) The majority of the resistors are trimmed prior to the attachment of the discrete components, using an air abrasive system. The high tolerance, high stability resistors required (top left hand corner of Figure 1) are glazed prior to trimming to increase their stability, to give protection from the encapsulating epoxy, and to warn the trimmer operator that extra care is required.The circuit produces rectangular pulses of set width at a repetition rate of the order of 15 kHz with a mark space ratio of 5:1. These parameters are determined by the time FIGURE Complete thick film hybrid circuit.
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