As discussed in [7], there are several issues in process variabilStatistical static timing analysis (SSTA) has been a popular research ity modeling and characterization, which may impede modeling for topic in recent years. A fundamental issue with applying SSTA in a statistical static timer. Statistical process characterization demands practice today is the lack of reliable and efficient statistical timing tremendous silicon and test resources and hence, is usually not done models (STM). Among many types of parameters required to be care-frequently. Careful tracking of parameter variations over time can be fully modeled in an STM, spatial delay correlations are recognized as overly expensive, which leads to gradual decrease in accuracy of a having significant impact on SSTA results. In this work, we assume process variability model. Moreover, there are other sources of varithat exact modeling of spatial delay correlations is quite difficult, and ability such as environmental sources of variability and systematic propose an experimental methodology to resolve this issue. The mod-layout-dependent variability which may be hard to characterize early propos accuracy e uirmental m rethodoloy to olvhing iSSu. timpose up-in a design cycle. These issues, due to either economic reasons or eling accuracy requirement is relaxed by allowing SSTA to imoeu-methodology-related reasons, make worst-case modeling favorable, as per bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from modeling just the worst-case bounds reduces the inter-dependency bepath delay testing on silicon. We utilize SSTA as the platform for tween process characterization and timing modeling. learning and propose a Bayesian approach for leaming spatial delay Among the many types of parameters that need to be carefully concorrelations. The effectiveness of the proposed methodology is illus-sidered to develop an STM, spatial correlations are recognized to have trated through experiments on benchmark circuits. significant impact on design timing [8,9], and hence on SSTA analysis Categories and Subject Descriptors: B.8.2 [Hardware]: Performance results [2,3]. Characterizing spatial correlations across device and inand reliability terconnect parameters (such as Leff, Vth, ILD) can be complex and resource consuming [10]. Moreover, it is not entirely clear how to effectively model (or aggregate) spatial correlations based on parameters Keywords:Statistical timing, Bayesian leaming, delay correlations of devices and interconnects [10] into the spatial correlations based on delay elements at the cell level [2] [3] for efficient cell-based SSTA. In 1. MOTIVATION OF THEWORK addition, correlations may exist between different parameters, which Statistical static timing analysis (SSTA) has attracted much atten-can further complicate the modeling issues [10]. tion in recent years (for example [1-6]). SSTA is attractive because Path delay testing traditional worst-case corner timing analysis h...
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