A ferroelectric-based (FE-based) non-volatile flipflop (NVFF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6fLs for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr,Ti)03(PZT) thin films.
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