We propose a balanced Pre-Charge Static Logic (PCSL) circuit style for asynchronous systems, and compare it against other reported circuit styles to counteract differential power analysis (DPA). Our study shows that all these circuit styles (including our balanced PCSL) dissipate different energy due to data-dependency, and hence balancing the energy of circuits embodying these circuit styles remains challenging. However, in view of low circuit overheads and asynchronous operations (with noise generation), our balanced PCSL is still competitive in terms of DPA-resistance, requiring 3.5× less power traces than its NULL convention logic counterpart.

We propose a Multiplexer Look-Up-Table (MLUT) based Substitution-Box (S-Box) implementation for the Advanced Encryption Standard (AES) algorithm. There are two key features in the proposed MLUT based S-Box. First, it is implemented based on 256-byte to 1-byte multiplexer with a 256-byte memory instead of the conventional implementation of employing multiplication inversion in GF(2 8 ) and affine transformation. Thus, our proposed S-Box is simpler in circuit implementation and lower in power dissipation. Second, our S-Box is 30× more secured against the Side Channel Attack (SCA) based on Correlation Power Analysis (CPA), as our proposed S-Box exhibits smaller variance in its power dissipation profile for different processed data. Based on the measurement results of AES-128 implemented on the Sakura-X FPGA board, our proposed S-Box dissipates only 1.9mW and features 5.5× lower power than the conventional S-Box implementation. Our proposed MLUT S-Box design is also highly secured as the CPA attack on the AES with our proposed S-Box implementation requires 13540 power traces. This is significantly higher than the conventional S-Box which requires only 445 power traces to uncover the same secrete key.

We propose a low area overhead and power-efficient asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) Sense-Amplifier Half-Buffer (SAHB) approach with quad-rail (i.e. 1-of-4) data encoding. The proposed quad-rail SAHB approach is targeted for areaand energy-efficient Asynchronous Network-on-Chip (ANoC) router design. There are three main features in the proposed quad-rail SAHB approach. First, the quad-rail SAHB is designed to use 4 wires for selecting 4 ANoC router directions, hence reducing the number of transistors and area overhead. Second, the quad-rail SAHB switches only 1 out of 4 wires for 2-bit data propagation, hence reducing the number of transistor switchings and dynamic power dissipation. Third, the quad-rail SAHB abides by QDI rules, hence the designed ANoC router features high operational robustness towards Process-Voltage-Temperature (PVT) variations. Based on the 65nm CMOS process, we use the proposed quadrail SAHB to implement and prototype an 18-bit ANoC router design. When benchmarked against the dual-rail counterpart, the proposed quadrail SAHB ANoC router features 32% smaller area and dissipates 50% lower energy under the same excellent operational robustness towards PVT variations. When compared to the other reported ANoC router, our proposed quad-rail SAHB ANoC router is one of the high operational robustness, smallest area, and most energy-efficient designs.

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM

We report a security analysis of the asynchronous-logic (async) quasi-delay-insensitive (QDI) Weak-Conditioned Half-Buffer (WCHB) cell approach against the side-channel differential power analysis (DPA) attack. When compared to the synchronous-logic (sync) standard cell approach, the WCHB cell approach is more power-balanced during the logic switching due to the unique features as follows. First, the WCHB cell approach embodies dual-rail data-encoding scheme, featuring more balanced power dissipation for different output transitions. Second, the WCHB cell approach embodies a power-constant input detector that validate the input-completeness, featuring more balanced power dissipation for different input combination. Based on 65nm CMOS process, the standard and WCHB cell approaches are simulated for 7 library cells, and compared in terms of the normalized energy deviation (NED) and normalized standard deviation (NSD). Nonetheless, the WCHB cell approach features 62% lower NED and 69% lower NSD than the standard cell approach.