The boundary scan logic for testing was developed in order to make the process of testing easier for System-on-Chip (SoC) [1] architectures. The proposed work focuses on designing a boundary scan logic for a 64-bit floating-point subtractor unit. The TAP controller designed is capable of executing the three mandatory Joint Test Action Group (JTAG) instructions of the IEEE 1149 standard. The testing architecture has the potential to not only test the functionality of the core logic but also to test single stuck-at faults for all the inputs and outputs of the core logic. A provision for bypassing the core logic was made in order to skip the IC while testing numerous ICs together. A simulation was also performed to demonstrate the above procedures. The designed module can further be used in a larger circuit with other ICs [2]containing a similar boundary scan structure with individual TAP controllers.
The traffic in wireless networks has been showing an exponential growth over the last decade. In order to meet the demand, and support a continuation of this growth, bandwidth efficient, high data rate and multipath fading free communication system is required. Orthogonal frequency division multiplexing (OFDM) system with multiple input multiple output (MIMO) configuration fulfils the above demands. In the process of generation of MIMO-OFDM signal, binary data is passed through a turbo encoder and the output of the turbo encoder is modulated using Quadrature Amplitude Modulation (QAM). The QAM output is passed through Inverse Fast Fourier Transform (IFFT) to produce OFDM signal and this signal is transmitted using Space Time Block Codes (STBC) for MIMO implementation. In this project, the MIMO-OFDM signal is detected by using maximum likelihood (ML) method in which Viterbi Algorithm is used. This project presents how the OFDM signal is generated at the transmitter and detected at the receiver using ML method. Results are simulated using MATLAB software.
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