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The heteroepitaxial growth of 3C‐SiC on Si(001) substrates has been studied in a hot‐wall‐type low‐pressure reactor. The Si substrates were carbonized by C2H2 prior to the SiC growth process to suppress the undesirable effects of lattice mismatching between Si and 3C‐SiC. A single‐crystal carbonized layer (3C‐SiC) was obtained from 500 °C to higher than 1000 °C in an C2H2 environment. Following the carbonization process, SiH2Cl2 and C2H2 were alternately supplied into the reaction tube to grow an epitaxial 3C‐SiC film. The growth rate of 3C‐SiC depended on the amount of Si incorporated into the surface of the substrates by H2 reduction of SiCl2 as a Si precursor. The “H2 intermittent flow” method employed during the SiC growth process efficiently suppressed the reduction of SiCl2 and induced a constant growth rate of the SiC. The crystallinity of the grown 3C‐SiC films on Si substrates was evaluated using transmission electron microscopy, selected‐area electron diffraction, and X‐ray diffraction methods. The grown 3C‐SiC films included anti‐phase boundaries and twins. The concentration of these plane defects decreased due to coalescence with each other during SiC growth and resulted in an improvement in crystallinity and electrical properties.

The planar defect density of 3C‐SiC can be reduced by growing it on undulant‐Si substrates. However, specific stacking faults (SFs) remain, that expose the Si‐face on the (001) surface. These residual SFs increase the leakage current in devices made with 3C‐SiC. They can be eliminated using an advanced SF‐reduction method called switch‐back epitaxy (SBE) that combines polarity conversion with homoepitaxial growth. Vertical metal–oxide–semiconductor field‐effect‐transistors (MOSFETs) are fabricated on 3C‐SiC with SBE, varying in size from a single cell with an area of (30 × 30) μm2 to 12,000 hexagonal cells on a (3 × 3) mm2 chip. The MOSFET characteristics suggest that currents greater than 100 A are realistic for blocking voltages of 600–1,200 V by increasing the number of cells with reduced cell‐pitch. The combination of blocking voltage capability with a demonstrable high current capacity shows that 3C‐SiC is well‐suited for use in vertical MOSFETs for high‐ and medium‐power electronic applications. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

The planar defects that occur at the 3C-SiC/Si(001) interface can be classified as anti-phase boundary (APB) and stackingfault (SF). In order to reduce SFs and APBs simultaneously, 3C-SiC is grown on undulant-Si in which the surface is covered with continuous slopes oriented in the [110] and [1 1 0] directions. This eliminates APBs at each slope of an undulation via step-flow epitaxy. In addition, SFs with an exposed C-face on the (001) surface (SF C ) are eliminated via self-vanishing, while those with an exposed Si-face on the (001) surface (SF Si ) form triangular shapes that expand with increasing 3C-SiC thickness. To remove any SF Si that cannot be eliminated on the undulant Si, an advanced SF reduction method involving homoepitaxial growth, called switch-back epitaxy (SBE), is investigated.

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A single-crystal β-Ga2O3 substrate was directly attached to a polycrystalline SiC (poly-SiC) substrate using a surface-activated-bonding method to enhance heat extraction from β-Ga2O3 devices. The effective thermal conductivity of the n+-Ga2O3/n+-poly-SiC bonded substrate and the electrical resistance at the heterointerface were characterized by using periodic heating radiation thermometry and analyzing vertical current–voltage characteristics, respectively. Small thermal and electrical resistances at the bonded interface demonstrated the strong prospects of the bonded substrates for applications to high-power vertical Ga2O3 devices.

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