A 0.18 mm CMOS 5 GHz quadrature voltage-controlled oscillator (QVCO) is demonstrated by using trifilar transformer coupling. The trifilar transformers composed of one primary coil and two secondary coils are used to separate the gate and drain bias for output voltage swing optimisation and also replace a conventional transistor-coupling method for quadrature output generation simultaneously. As a result, the trifilar-coupling QVCO achieves 180.1 dBc/Hz figure of merit (FOM) at the supply voltage of 1.2 V. The on-chip passive single sideband upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Thus, a 33.7 dB sideband rejection ratio is achieved.
This paper proposes a true 50% duty-cycle highspeed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 µm SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.Index Terms -50% duty cycle, divide-by-N, prescaler, SiGe HBT.
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