The deployment of RFID technology will gain a significant boost if indoor location positioning is incorporated into RFID systems. Recent development in range estimation indicates that phase difference of arrival (PDOA) shows a promising performance. PDOA technique suffers from an inherited limitation of phase difference which is restricted to the maximum of 2π radians. In this paper a robust algorithm to overcome this limitation and unwrap the phase is presented. A theoretical model has been developed to accurately unwrap the phase using the round trip time of flight. Simulation results show that the proposed method can be used to estimate the range even under significant Round Trip Time of Flight (RTTF) measurement error. It is shown that a wide range of time measurement errors can converge to actual distance if the frequency difference of the transmitted waves is properly selected.
A new readout and self-test circuit for MEMS devices is presented in this paper. A Phase Locked Loop (PLL) has been utilized to convert variations of MEM capacitance to time domain signals. The proposed scheme presents a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Simulation results in Cadence environment using TSMC CMOS 65nm technology indicate that a measurement resolution of 73aF can be achieved.
In this paper, we propose a simplified Log-MAP algorithm that is equivalent to the Log-MAP algorithm in terms of the bit-error-rate (BER) performance, but without its implementation difficulties. The proposed algorithm is based on a linear approximation of the correction function in the Log-MAP algorithm over different signal-to-noise ratio (SNR) regions. This approximation is simple to implement by avoiding the number of complicated operations. Simulation results demonstrate that this simplified algorithm can achieve the same BER performance as the Log-MAP algorithm.
A new readout circuit for MEMS devices is presented in this paper. A Phase Locked Loop (PLL) has been utilized to convert variations of MEM capacitance to time domain signals. The proposed scheme presents a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Simulation results in Cadence environment using TSMC CMOS 65-nm technology indicate that a measurement resolution of 73 aF can be achieved.
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