Exploring architectures for large, modern FPGAs requires sophisticated software that can model and target hypothetical devices. Furthermore, research into new CAD algorithms often requires a complete and open source baseline CAD flow. This article describes recent advances in the open source Verilog-to-Routing (VTR) CAD flow that enable further research in these areas. VTR now supports designs with multiple clocks in both timing analysis and optimization. Hard adder/carry logic can be included in an architecture in various ways and significantly improves the performance of arithmetic circuits. The flow now models energy consumption, an increasingly important concern. The speed and quality of the packing algorithms have been significantly improved. VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. We also release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments. Finally, we show that while this version of VTR supports new and complex features, it has a 1.5× compile time speed-up for simple architectures and a 6× speed-up for complex architectures compared to the previous release, with no degradation to timing or wire-length quality.
Nowadays Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the workflow.ii CONTENTS
Many modern programming languages rely on memory management environments that are responsible for allocation and deallocation of objects. Garbage collection phases are used in order to detect inaccessible objects on the heap so they can be deallocated. The performance of garbage collection techniques depends heavily on the environment, implementation specific parameters and the benchmark used. The contribution of this publication is an extendable memory management simulator, which aims to assist developers in memory management evaluation and research. The simulator is capable of reading operations from a trace file extracted from a virtual machine and simulating the memory management needed by the simulated mutator. The framework aims to provide an isolated experimentation and comparison platform in the field of automatic memory management. New algorithms can be added to the framework in order to compare them to established algorithms.
SUMMARYSome Java programs lend themselves to being run many times and create the same fixed objects every time. Many of these common objects are Strings. To exploit this trend, we have modified IBM's J9 Java virtual machine (JVM) to allow the same String objects to share (reuse) their internal char[] (character) arrays in each JVM. The first instance of the Java program runs to completion and then sets up the Strings for sharing, so that subsequent instances of the same program can use the char[] arrays that it created instead of recreating them. String sharing will not provide benefit in all applications, but for those that fit the pattern, as exemplified by the Eclipse and H2 benchmarks, we were able to achieve significant heap saving with negligible impact on performance.
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