Visualization support for FPGA architecture exploration

Abstract

Nowadays Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the workflow.ii CONTENTS

VTR 7.0

“…ODIN now includes a tool to visualize the gate-level structure of the design early in the flow; users can interactively highlight blocks or paths and show logic values generated by the ODIN II simulator [Nasartschuk et al 2012]. This tool helps FPGA architects understand the design structure and helps ODIN II developers test and debug new elaboration features.…”