Bandwidth design is described for the amplifier and reshaping circuit that determine the receiving sensitivity of a digital optical repeater. Also described is the optimum adjustment of the operating conditions as determined by the combination of the amplification factor of an APD and the discrimination level. For the former, the required conditions are clarified for the clamp circuit as a low‐cut circuit. the relations are obtained between the peak value variation of the output voltage of the clamp circuit and the bandwidth of the reshaping circuit. For operating condition adjustment the repeater operation is formulated under various degradations and the relation between the causes of degradation and the SNR is analyzed. Based on these findings, various adjustment procedures are compared. It is shown that the system has sufficient tolerance to these degradations if adjustment is made for intersymbol interference.
The present study provides a basis for choosing the conditions for the clamp circuit as a low‐cut circuit and the bandwidth for the reshaping circuit. A method of adjusting the operating condition is found that provides sufficient tolerance to degradation of an optical repeater.
Design philosophy of a fiber optic transmission line terminal circuit (LTC) module for digital subscriber loops is described. A small, cost effective LTC module has been developed that realizes a 52 to 156 Mb /s fiber -to-the -home system. The salient points are ; various combinations of LDs and PDs /APDs can be used to match the subscriber line length requirements, CMI or scrambled NRZ line codes can be used, the module is suitable for single mode fiber (SMF) or graded index fiber (GIF) cables, high density LSI techniques can be used to develop single chip components.The volume of the contructed module is 92.6cm3 with a dispersion power of 3W. A single low power IC chip has been developed that includes decision and timing circuits. Thus timing phase adjustments are not needed. Differential amplification created between the pre -amplifer IC and the main amplifier IC is employed to yield a high common mode rejection ratio and suppress the effects of external noise. The double loop of the auto-powercontrol (APC) for the LD is adopted to separately control the d.c. bias current (In) and the pulse modulation current (IP). The CMI -CODEC -IC is fabricated by a Bi -CMOS process. It includes a PLL circuit that doubles input clock frequency for CMI signal coding.The CMI line code can be adopted to maintain bit sequence independence, facilitate hardware implementation of the timing-extraction circuit, and prevent bit errors caused by received optical power fluctuations. Received optical power fluctuations can happen when fibers are manually handled during cable installation or mid -span branching.
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