Distributed hash tables are increasingly being proposed as the core substrate for content delivery applications in the Internet, such as cooperative Web caches, Web index and search, and content delivery systems. The performance of these applications built on DHTs fundamentally depends on the effectiveness of request routing within the DHT. In this paper, we show how to use soft state to achieve routing performance that approaches the aggressive performance of one-hop schemes, but with an order of magnitude less overhead on average. We use three kinds of hint caches to improve routing latency: local hint caches, path hint caches, and global hint caches. Local hint caches use large successor lists to short cut final hops. Path hint caches store a moderate number of effective route entries gathered while performing lookups for other nodes. And global hint caches store direct routes to peers distributed across the ID space. Based upon our simulation results, we find that the combination of the hint caches significantly improves Chord routing performance: in a network of 4,096 peers, the hint caches enable Chord to route requests with average latencies only 6% more than algorithms that use complete routing tables with significantly less overhead.
We have developed a general purpose evolutionary algorithm testbed (GPeat) that allows evolutionary algorithm designers to quickly and with minimal hardware knowledge move their algorithms into hardware. A user programs the testbed through a graphical user interface (GUI) that lets the user choose system parameters such as types and combinations of crossovers and mutations, initial population descriptions, fitness function rules, criteria for selection and elitism rates. A variety of sensors or computer connections can be made to the testbed so that both intrinsic and extrinsic runs can be carried out. Outputs of the testbed can likewise be computer or device directed. Use of the GUI requires minimal knowledge of hardware and connecting sensors and output devices to the board requires only the ability to identify basic device characteristics (i.e. voltage or current output, analog or digital output). In this first version, sensor inputs, fitness/chromosome value pairs, generated initial values, selected outputs are dumped to a file on the computer for analysis. New evolutionary algorithm specific hardware structures have also been developed which can provide faster run times than direct FPGA implementations. This tool will allow quick prototyping for those wanting to move their algorithms from the computer to the real world, the option to use the hardware as a debugging tool or as the final embedded, portable evolutionary algorithm hardware system.
We developed a "General Purpose Evolutionary Algorithm Testbed" through which a wide variety of evolutionary algorithms can be implemented in hardware, quickly and with a little hardware knowledge. A user interface allows the user to enter parameters needed to choose evolutionary algorithm components such as type of encoding, initial population description, selection type, reproduction type and the type of
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