Analysis of the biological properties and use of comparative genomic hybridization to locate chromosomal aberrations in the human testicular seminoma cell line JKT-1 and its highly metastatic cell line JKT-HM Y. JO, K. KINUGAWA, T. MATSUKI, M. MORIOKA and H. TANAKA Department of Urology, Kawasaki Medical School, Kurashiki, JapanObjective To examine the biological properties, and utilthe lung and lymph nodes in all five mice by 50 days.The in vitro tumour cell invasion and animal assays ity of comparative genomic hybridization (CGH) to locate chromosomal aberrations, in a new human suggested potential invasion and metastasis of JKT-HM. The DNA index was 1.48 for JKT-1 and 1.50 testicular seminoma cell line, JKT-1, and a highly metastatic cell line, JKT-HM, developed as an animal for JKT-HM. CGH analysis revealed various chromosomal aberrations undetected by examining their karymodel of spontaneous metastasis. Materials and methods JKT-HM was isolated by transotypes, e.g. loss of 18p, Yq and gain of Xq, and the technique has potential to detect genetic aberrations planting cells of JKT-1 into the dorsal skin of nude mice, using methods developed previously. The biologirelated to metastasis in this model. Conclusions The two cell lines JKT-1 and JKT-HM, and cal properties of JKT-1 and JKT-HM cells were examined using assays of cell proliferation and in vitro the metastatic animal model used, were useful in studying human testicular seminoma and the metatumour cell invasion, and the DNA index (by flow cytometry). CGH was used to analyse chromosomal static behaviour of cancer. In addition, CGH was useful for analysing the chromosomes of two diCerent cell aberrations and to detect chromosomal regions causing metastasis in the testicular seminoma cell lines.lines derived from the same parent line. Keywords Testicular seminoma, cell lines, comparative Results The JKT-1 and JKT-HM cells showed no diCerence in morphology or cell proliferation. After transgenomic hybridization, karyotype, metastatic model, mouse planting JKT-HM into mice, the cells metastasized to established a germ-cell tumour cell line through the
IntroductionIt has been already clarified that, in down scaling of device dimensions, power-supply voltage (Vcc) for CMOS devices can be reduced from 5V to 2.5V without sacrificing performance trend ancl device reliability [']. Moreover, an operating voltage must be steadily reduced from power dissipation point of view, according to prospect for future CMOS design in deep-submicron era. On the other hand, the various CMOS chips for battery back up system such as a watch, a portable radio and stereo already exist at 1-1 5V operation. However, such CMOS chips compromise their performance, since the threshold voltage is constant for any generation chips, in order to preserve standby power. Therefore, a new device design is required in order to offer low voltage operated CMOS device without any speed loss.111 this paper, design method for high performance deepsubmicron CMOS operated at around 1V has been proposed, together with discussion on threshold voltage limitation and suppression of parasitic effects. Based on above consideration, a 1V operated 0.15pm CMOS was fabricated and evaluated. As a result, 50psec at 1V operation for the CMOS ring oscillator at room temperature has been verified. Figure 1 shows threshold voltage (Vth) dependence of the gate delay time of the CMOS inverter with F/O=l. As Vth approaches toward Vcc, delay time increases rapidly corresponding to drastic reduction of MOSFET's current. It is necessary to decrease the threshold voltage as low as possible to achieve high circuit performance. On the contrary, lowering Vth causes large increase of standby power as shown Fig.2. However, high speed application can accept standby power below O.lW, since a high speed cblip does not require battery back up use. Vth reduction also cau!;es insufficient noise margin. Figure 2 shows lower limit of the threshold voltage determined by noise margin (NM), which was defined as (Vo -VoL) /(VIH-VIL) and simulated with Sodini for various%cc. As c early indicated in Fig.2, the threshold voltage can be lowered with reduction of power supply voltage, ancl the lower limit is about 15% of Vcc. Reduction of Threshold Voltage for Low Voltage Operation Parasitic Capacitance and ResistanceThe parasitic capacitance of CMOS LSI consists of junction capacitance C,, gate oxide capacitance CO,, and wiring capacitance Cw. Figure 3 shows power-supply voltage dependence of the percentage that each parasitic capacitance shares in typical load capacitance of LSI circuits. C is inversely proportional to square root of 'Jcc, while CO, and dw do not depend on it. As a result, the total parasitic capacitance 1s Increased, and further, C, becomes one of the dominant parasitics with lowering operation voltage. Therefore, reduction of C, is a key issue for achieving high speed circuit operation at low voltage such as 1V. In order to reduce (Z,, 'spot punch through stopper ion implantation' can be introduced. The implantation is adjusted to junction depth and restricted xverly under channel area, excluding junction area, as shown in Fig.4....
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