Abstract. In this paper a set of high-speed differential pad cells are presented. The pad cells are designed to work with the IEEE Draft Standard for Low-Voltage Differential Signals for Scalable Coherent Interface (SCI-LVDS) [4~. The standard sets specifications for high-speed point to point communication between complex subcircuits in digital systems. The pad cells are in compliance with the draft, but are designed to operate up to at least 500 MHz instead of the 250 MHz proposed in the draft. The pad cells presented in this paper are designed in a standard 1 #m CMOS process using standard DIL packaging. This has proved possible despite the electrical specifications being narrowed as a result of the doubling of the operating frequency. The circuit has ESD protection and utilizes internal termination with a single external impedance reference and thereby facilitates ease of use and higher package density.
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