As the development of technology node, ULK was used as isolation material in Cu damascene integration. ULK is a porous material with low mechanical strength and low adhesion. During CMP process, slurry additive and moisture will enter the hole of ULK material and result in the increasing of ULK K value, and also ULK film is easily damaged by mechanical force. To solve this problem, a capping layer is designed in Cu integration. In this paper, a novel barrier is developed to meet this integration need. Slurry chemistry/additives effect on RR selectivity and topo is evaluated in this paper.
Novel CuCMP slurry was evaluated under different polishing conditions and its impact on topography, thickness and in line test performance was investigated. Generally, topography, such as dishing and erosion, results from over-polishing after Cu polishing step and it can be modified and reduced by fine tuning process parameters. Firstly, different Cu polishing condition has been attempted to produce different topography for barrier polishing to compensate in order to cater for different integration scheme with different oxide material. Secondly, topography can be modified by barrier polishing condition due to high selectivity slurry is used during barrier polishing. Longer polishing time can cause Cu protruded in narrow dense arrays. Electrical data shows Cu polishing overpolishing time has impact on Rs, and longer overpolishing results in higher Rs, as well as high head/platen rotation speed.
As the technology node is advanced to 28nm and below, several new materials are introduced such as ultra low-k dielectric and metal hard mask. This presents critical chalenges to Cu-CMP in terms of k-shift, poor within-die uniformity and deteriorated breakdown voltage. Such issues must be resolved before moving to mass production. This paper presents a practical solution with improved barrier slurry and process for high performance of ULK/Cu interconnects at the advacned technology node. Through balancing the removal rates of various films, the reasonable topography is obtained. Slurry formulation refinement and post-CMP treatment are applied together to recover k value and to improve within-die range under optimized process conditions. While the surface property and breakdown voltage of the metal layer have been studied, it's found that post-polish cleaning in combination with CMP slurry plays a major role to enhance reliability.
Cu capping layer deposition plays an important role in BEOL plasma induced damage. In this paper, PID issue by Cu capping layer deposition process studied. The PID performance was studied with Cu capping layer deposition recipe optimization. And, the impact on PID performance of different Cu capping layer equipment was also compared. The PID performance is different with antenna ratio increase, both NMOS and PMOS PID performance with different antenna ratio have been investigated. In order to get clear supporting evidence for plasma damage, plasma charged voltage of wafer surface is also studied by Quantax in this paper. Finally we developed an optimized Cu capping layer deposition process with acceptable PID performance and without any reliability degradation. IntroductionWith the IC technology development to more advanced, gate oxide thickness is scaled down, and plasma induced damage can potentially degrade oxide integrity significantly. Plasma Induced Damage (PID) is one of the most important concerns in both front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) process development. Therefore, how to evaluate and minimize the plasma damage becomes much more important. In particular, the degradation of thin gate oxide is accelerated by the collection of charge on the electrically floating gate electrode. The charge build-up mechanism is called the "antenna effect". In this paper, we will focus on studying BEOL copper capping layer(SICN) process on PID issue. We use two comb type antenna layouts to study PID performance from copper capping layer film(SICN) process with 5000:1 and 10000:1 antenna ratio(AR) both on NMOS and PMOS. In order to get clear conclusion, we also study PID performance with one layer or multi-layers(metal 1 to metal 6) SICN process. Especially for multi-layers process, gate oxide will endure cumulative plasma damage from every layer and PID issue will be enhanced. And Voltage on blanket wafer post DB process is also studied for supporting evidence in this study.
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