This paper presents a technique for designing CMOS high-speed state machines with a clock frequency ranging from DC to greater than 130MHz in 1.2-prn technology. This technique applies weak feedback to known high-speed dynamic circuits to achieve both static and high-speed capability. Two-phase nonoverlapping clocking is used to eliminate any possible races. Propagation delays of critical paths are minimized by performing their logic functions within the master stage of the flip-flops.klntrpducQon Traditional high-speed CMOS techniques have placed emphasis on dynamic circuits. A dynamic CMOS logic gate is roughly twice as fast as a static full complementary CMOS gate [l].[2] and [3] introduced techniques for designing high-speed dynamic circuits in excess of 200 MHz in a 3-prn CMOS process including dynamic latches and dynamic edge triggered flip-flops using single-phase clocking. However, these techniques require a minimum specified clock frequency. In the case of single-phase clocking, the clock must be specified with a maximum allowable rise and fall time.Some designs require the speed of dynamic circuits without the constraints of dynamic circuits. To avoid these constraints, a static, pseudo-dynamic technique is applied to the circuits proposed in [2] and [3], and a two-phase nonoverlapping clocking scheme is used. Section I1 of this paper discusses this static pseudo-dynamic technique and Section 111 describes the two-phase clocking strategy.Flip-flops with built-in logic functionality can be constructed using the circuits proposed in [3] making them ideal for state machine design. Section IV details how to build state machines using these flip-flops, and experimental results of a 4-bit counter will be presented. Section V discusses the actual application of these techniques for designing a controller for an optically pulsed phase locked loop, called the OPPLL chip. Finally, conclusions are presented in Section VI.
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