The traditional wafer level packages (WLPs) are fan-in redistribution layer (RDL) lay-out design; it may not be able to meet the high pin-count handheld device requirement. So the new fan-out wafer level packages (FOWLPs) are emerged in the last few years. The fan-out WLP starts with the reconfiguration dies on carrier and embeds die by molded compound. The molded reconstituted wafer forms a compound base to apply litho and metallization process, as in the conventional fan-in WLP back-end processes to form the packages.In this study, a new high-performance fan-out wafer level package (sWLP) is developed. Emphasis is placed on the fabrication process and material selection. Since FOWLP with molding process has warpage challenge, herein we use lamination process with dry film to embed dies and adhere with Si wafer on the backside to achieve a ultra low warpage. Also, package level and board level performance are determined by finite element analysis. Furthermore, package and board level reliability are estimated by the standard JEDEC standard. The package warpage behavior corresponding to temperature conditions is measured by moiré method. Some important results for the new package are summarized as below. Assembly process evaluation and improvement. Board level drop test performance and stress / warpage simulation. Shadow moiré measurement and thermal effect study. Reliability results of package level, including precondition, TCT, HTS and HAST.
Reliability results of board level, including drop test andTCT.
IntroductionAs a result of handheld device high density, high electrical performance, high thermal dissipation performance and multi functions requirement. Wafer Level packages (WLP) replace the traditional process of assembly without die bond, wire bond and molding and provide the ideal solution for high electrical performance and small form factor demand in handheld device applications.But typical wafer level packages (WLP) is fan-in redistribution design, it can not meet high pin count handheld device requirement. So fan-out Wafer Level Packages (FO WLP) has emerged in the last year. Molded FOWLP starts with the reconfiguration dies on carrier and embedded die by molded compound. The molded reconstituted wafer forms a
In new markets such as in-vehicle cameras, surveillance camera and sensing applications that are rising rapidly in recent years, there is a growing need for better NIR sensing capability for clearer night vision imaging, in addition to wider dynamic range imaging without motion artifacts and higher signal-to-noise (S/N) ratio, especially in low-light situation. We have improved the previously reported single exposure type wide dynamic range CMOS image sensor (CIS), by optimizing the optical structure such as micro lens shape, forming the absorption structure on the Si surface and adding the back side deep trench isolation (BDTI). We achieved high angular response of 91.4%, high Gr/Gb ratio of 98.0% at ±20°, 610nm, and high NIR sensitivity of QE 35.1% at 850nm, 20.5% at 940nm without degrading wide dynamic range performance of 91.3dB and keeping low noise floor of 1.1e-rms.
This paper presents a robust optical disc discrimination method which tolerates pick-up head and laser power source deviations.Unlike the prior art techniques, the proposed method uses normalization process to cancel influences caused by deviations of pick-up heads and laser power source so as to minimize the disc discrimination error rate to secure normal disc playback function of an optical disc drive.
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