Keisuke Korekado scite author profile

et al. 2003

Abstract. Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a convolutional network VLSI architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this approach merged/mixed analog-digital architecture. The VLSI includes PWM neuron circuits, PWM/digital converters, digital adder-subtracters, and digital memory. We have designed and fabricated a VLSI chip by using a 0.35 m CMOS process. The VLSI chip can perform 6-bit precision convolution calculations for an image of 100¢100 pixels with a receptive field area of up to 20¢20 pixels within 5 ms, which means a performance of 2 GOPS. Power consumption of PWM neuron circuits is estimated to be 20 mW. We have verified successful operations using a fabricated VLSI chip.

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An image filtering processor for face/object recognition using merged/mixed analog-digital architecture

et al.

Face position detection by a convolutional neural network using an image filtering processor VLSI

International Congress Series

et al. 2006

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition

et al. 2004

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture

IEICE Transactions on Electronics

et al. 2006