Abstract-This paper presents a new NoC architecture to improve flexibility and area consumption using a centralized controller. The idea behind this paper is improving SDN concept in NoC. The NoC routers are replaced with small switches and a centralized controller doing the routing algorithm and making control decisions. As one of the main desirable property of NoC is flexibility, in this work with the help of centralized controller, having different topologies and also having two separate networks in a single platform is possible. The other effects of this new scheme are power and area consumption which are investigated. Performance of the NoC is also studied with an analytical model and compared with the traditional NoC. The proposed NoC is implemented in VHDL, simulated and tested with ISE Xilinx.Index Terms-Network on chip (NoC), software define network (SDN), centralized controller, flexibility, reconfigurability.
Abstract-Residue number system is a non-weighted integer number system which uses the residues of division of ordinary numbers by some modules for representing that ordinary numbers. In this paper, the general three moduli set }2 n -1,2 n +1,2 pn+1 -1} based on CRT algorithm is proposed in which -p‖ is an even number greater than zero. The special case of this set for p=2 which is }2 n -1,2 n +1,2 2n+1 -1{ is also described in this paper. Since the dynamic range of this set is odd, some difficult problems in RNS can be easily solved based on this set using parity checking. The proposed reverse converter is better in speed and hardware in comparison to reverse converters in similar dynamic range. Moreover, from the complexity point of view, the internal arithmetic circuits of this moduli set is improved and is less complex than the other sets in similar dynamic range.
The performance growth in processors has been continuing toward increasing the number of processing cores on the chip and scaling the feature size of transistors. However, in the nano era, side effects of the scaling, such as induced heterogeneities in the performance, power, and soft error rate of identically designed cores, prevent the potential performance from being fully utilized. In this paper, we harness the mentioned side effects in shared-memory multicore processors with unpredictable workloads by a dynamic heuristic scheduling algorithm called HDSAP. The aim of HDSAP is to maximize performance, i.e. the average response time, under power and reliability constraints in presence of induced heterogeneities. In this regard, we use a mathematical model to quantify task to core assignments based on performance variation. We also consider the variation in power to change selected cores when the power constraint is missed. To meet the reliability constraint, we use N-Modular redundancy while being aware of the variation in soft error rate of cores to prevent under/over reliability estimation. To evaluate HDSAP, we run SPLASH benchmark suite on Sniper and MACPat simulators. As a result, the response time of HDSAP reduces by 6%, 8%, and 25% in comparison with similar algorithms under the same power and reliability constraints.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.