Multivalued logic circuits, which can handle more information than conventional binary logic circuits, have attracted much attention as a promising way to improve the data-processing capabilities of integrated circuits. In this study, we developed a ternary inverter based on organic field-effect transistors (OFET) as a potential component of high-performance and flexible integrated circuits. Key elements are anti-ambipolar and n-type OFETs connected in series. First, we demonstrate an organic ternary inverter that exhibits three distinct logic states. Second, the operating voltage was greatly reduced by taking advantage of an AlO gate dielectric. Finally, the operating voltage was finely tuned by the designing of the device geometry. These results are achievable owing to the flexible controllability of the device configuration, suggesting that the organic ternary inverter plays an important role with regard to high-performance organic integrated circuits.

Negative differential resistance (NDR) has large potential for versatile device applications, including high‐frequency oscillators, memories, fast switches, and multilevel logic circuits. NDRs are observed at heteromaterial interfaces in resonant tunneling diodes or Esaki diodes consisting of compound semiconductors or two‐dimensional (2D) atomic thin films. However, these devices suffer from poor peak‐to‐valley ratios (PVR) at room temperature; a cryogenic temperature is needed to improve the PVR. These negative factors are obstacles to practical applications. Here, a new NDR transistor is proposed, in which a p‐n heterojunction of organic semiconductors plays a key role. Well‐balanced carrier transport is manipulated at the organic p‐n junction to realize outstanding NDR. Experimental and simulation analyses reveal that the observed NDR can be explained by analogy with the shoot‐through current mechanism in complementary metal‐oxide‐ semiconductor (CMOS) devices. As a result, the NDR transistor shows large PVRs of up to about 104 even at room temperature.

The key concept behind this study is the use of “geometry engineering” to elucidate the carrier transport path and to control the device properties of organic antiambipolar transistors. Investigations of carrier transport properties with different device geometries, such as the pn-heterojunction length and the channel layer thickness, revealed that charge carriers transported through the lateral edge junction between p- and n-type channels. We also found that the peak voltage was effectively reduced from −49 to −39 V in a device with asymmetric channel lengths. These results suggest that device performance can be enhanced by taking advantage of the designability of the device geometry, which can employ the strong features of organic antiambipolar transistors.