We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time.Index Terms-Dielectric breakdown, electron beams, failure analysis (FA), inspection, integrated circuit (IC) manufacture, leak detection, logic devices, SRAM chips, voltage measurement.
We studied the VC (Voltage Contrast) enhancement technique of the FA (Failure Analysis) tool We found a gate leak VC dependency on the relative angle between the beam scan direction and gate electrode direction. A simplified RC model can explain this phenomenon qualitatively. With the help of this VC enhancement technique of the FA toolt we could tune the EBI recipe in appropriate sensitivity. As a result, correct EBI evaluation results of countermeasure experiments led us to a solution within a shorter period oftime.
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