We are currently developing an inspection system that will provide a low-cost means of screening prior to shipment by fully visualizing latent 1SSF (single Shockley stacking fault) defects originating from basal plane dislocations (BPDs) that cannot be detected by current defect inspection systems. The system will capture not only the defects that expand into right triangles under relatively low-level forward bias, but also the defects that expand into more serious bar-shaped 1SSFs under relatively high-level forward bias, with a particular focus on capturing TED (threading edge dislocation)-converted BPD at or below the buffer layer/substrate interface. Since these defects are known to cause forward voltage degradation during device operation, so-called "burn-in" (accelerated current stress) screening operation is currently utilized in some device manufacturers to avoid the shipping of the defective devices, but it is very time-consuming process which raises a total cost of production. The system we are developing, which can significantly reduce the screening time, has the potential to replace the "burn-in" operation.
In the previous report [1], we proposed the S-EVC (Selective Expansion-Visualization-Contraction) method (Fig. 1) that effectively screens for malignant BPDs (basal plane dislocations) in the drift and buffer layers, which expand to SSFs (Shockley-type stacking faults), leading to forward voltage degradation. The method intentionally utilizes the REDG (recombination enhanced dislocation glide) mechanism by UV (ultraviolet) irradiation in wafer sorting to replace the so-called burn-in (accelerated current stress) process, which is time-consuming during mass production. In the report, triangular SSFs were examined to verify the effectiveness of the method, but they only occupy a much smaller area of the active region on the chip than bar shaped SSFs. In this study, to improve the S-EVC method to be more practical, we focused on the more serious bar shaped SSFs which have a non-negligible impact on electrical characteristics. The bar shaped SSFs are mostly expanded from TED (threading edge dislocation)-converted BPD at or below the substrate epitaxial layer interface. In PL (photoluminescence) observation by a 710 nm LPF (long-pass filter), the TED-converted BPD and the complete TED extended from the bottom of the substrate are observed as the same dark spot, but it was confirmed that both can be distinguished by the presence or absence of their SSF expansion by UV irradiation. In addition, in order to confirm the validity of the S-EVC method even on the virgin epi wafer, UV irradiation was performed on both the aluminum doped PN structured wafer and the virgin epi wafer, and the similar SSF expansion was observed. Meanwhile, the correlation between UV irradiation and forward voltage degradation was quantified using PiN diodes by comparing the glide velocity of 30°Si (g) core partials for bar shaped SSFs by UV irradiation stress with that by current stress.
We propose the new practical and effective method, called Selective E-V-C (Expansion-Visualization-Contraction) technique, to screen out the basal plane dislocations (BPDs) which might cause the forward voltage degradation of SiC devices. Since the method can be adopted at the epi wafer receiving inspection process in early stage of production line, it may replace the very time-consuming so-called "burn-in" operation currently utilized in some device manufacturers.
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